Recently, with the spread of the internet and the spread of colour copiers, the market for digital still cameras that read photgraphic data directly into a personal computer (PC) has been growing rapidly.
A simple block diagram of a conventional digital still camera system is shown in FIG. 2. The internal processing of the digital still camera system will be described below referring to FIG. 2. In order to simplify the description, the digital still camera system will be referred to simply as a "camera" in the following.
Image information is taken in to the camera through a charge coupled device (CCD) a. Next, the image data that has been taken in is converted to a digital signal by an input section IC b, and taken in to a graphics memory e. It is common for cameras of intermediate quality or higher to use multiport DRAM or memory known as VRAM in a graphics buffer. This type of multiport DRAM is an internationally standardized memory having two ports, namely a DRAM port that operates exactly the same a general use DRAM, and a SAM port capable of serial access for displaying a picture on a CRT or liquid crystal screen etc.
Data taken in from the CCD can be supplied as a moving image seen through the eyes of camera user either as a video output via sequentially writing into the multiport DRAM, video encoder h, D-A converter i and buffer j, or actually seen on a liquid crystal panel k etc. This is the circuit operation when a picture taken by a television camera is immediately viewed on a television set and not transformed.
Further, in a general camera, there is a shutter in a key input section d, and from the time when a shutter key is caused to be pressed by a digital still container c comprising ROM, RAM, a micro processor core, and a timer, etc., CCD input from a is suspended, and image compression of image information that has been stored in the multiport DRAM (an image at the instant the shutter was pressed) is commenced.
The information stored in the multiport DRAM e is taken in as fixed block information, and the result of compression is temporarily stored in buffer memory f (a general purpose DRAM is generally used).
Here, the SAM port of the multiport DRAM keeps outputting video in the same way as before the shutter is pressed, even while the image information stored in the multiport DRAM is being compressed and transferred to the buffer memory f. At this time, new image information is not transmitted from the CCD, so an image output from the video camera is a still image (the compressed image is this outputted still image).
When this graphics memory does not have the above mentioned two port multiport DRAM, but uses a conventional general purpose memory such as a single port memory, there is no video output while an image obtained by pressing the shutter is being compressed, in other words, an image being viewed by a user is totally dark. Accordingly, the commercial value as a camera does not compare very favorably to a camera using a multiport DRAM.
When video output continues to be output while the shutter is pressed and image data is being compressed, without using this multiport DRAM, a new, separate image memory is currently necessary for image output. Also, as will be described later, in the future a method is being considered of replacing a general purpose DRAM and using an extremely fast synchronous DRAM (SDRAM), and carrying out image compression and video output in time division.
When this type of new separate memory for graphics is used, the mounting area on a port is increased, the number of components is also increased, and the cost therefore rises. Further, when an extremely fast synchronous DRAM (SDRAM) has been used, control becomes difficult, it is unavoidable that accesses to the memory are more than doubled (because compression and video output are carried out at two ports), guaranteeing an operating margin becomes extremely difficult, and the design of the controller is troublesome.
Next, the multiport DRAM e in FIG. 2 will be described in detail. FIG. 3 is a circuit diagram of a conventional multiport DRAM.
First of all, the function of signals input to the control signal generator I in FIG. 3 will be described. Control signals generated from the control signal generator I are actually input to each of the circuits shown in FIG. 3, but this has been omitted for simplification, and these signals control the access operation of the multiport DRAM. RAS/ is a row address strobe, CAS/ is a column address strobe, WE/ is write enable, DT/OE/ is data transfer and output control, SC is serial clock, and SE/ is a serial access enable signal.
Next, the connectional relationship of each element will be described.
As shown in FIG. 3, memory cell units Cij (i=1.about.n, j=1.about.m: where m, n are arbitrary integers), comprised of one memory cell capacitor and one transistor, are connected to a word line WLj (j=1.about.m: where m is an arbitrary integer), and one bit line of a bit line pair BLi, /BLi (i=1.about.n: where n is an arbitrary integer) being complementary signal lines.
Sense amplifiers SAk (k=1.about.n: where n is an arbitrary integer) are connected between the bit line pairs BLi, /BLi. Transistors Trai, Trai/ (i=1.about.n: where n is an arbitrary integer), constituting means for switching between the bit lines BLi, and /BLi, are connected between the left end portion of the bit line pairs BLi,/BLi and data buses D,/D.
Transistors Trbi, Trbi/ (i=1.about.n: where n is an arbitrary integer), constituting means for switching between the bit lines BLi,and/BLi, and transistors Trci, Trci/ (i=1.about.n: where n is an arbitrary integer), constituting means for switching between serial data buses SD, /SD, are connected in series between the right end portion of the bit line pairs BLi, /BLi and the serial data buses SD, /SD.
Flip-flops Fi (i=1.about.n: where n is an arbitrary integer), comprised of inverters connected in opposite directions, are connected between the point of connection of Trbi and Trcl, and the point of connection of Trbi/ and Trci/.
In this way, a column unit Ci (i=1.about.n: where n is an arbitrary integer) is made up of a memory cell unit Cij, the complementary signal lines constituting the bit line pair BLi, /BLi, sense amplifier SAk, transistors Trai, Trai/, transistors Trbi, Trbi/, transistors Trci, Trci/ and the flip-flop Fi.
When an address is input from the address terminals ADD, address generator D outputs a Y address YA. This Y address YA is input to Y decoder B, and the Y decoder B outputs a column unit select signal output YDi. This column unit select signal output YDi is a signal for switching Trai and Trai/.
An X address XA, being another output from the address generator D, is input to X decoder A, and this X decoder A selects a word line WLi.
The output section of address generator D is connected to the input section of serial address generator J, with this serial address generator J outputting a serial address SA and inputting this serial address SA to serial decoder F.
This serial decoder F outputs a column unit select signal output SDi for switching Trci and Trci/.
Data buses D, D/ are connected to input/output unit E having I/O terminals, while the data buses SD, SD/ arc connected to input/output unit G having SI/O terminals.
Next, the operation of the multiport DRAM of FIG. 3 will be described with reference to FIG. 4.
The operation of the DRAM will be described for each instant shown in FIG. 4.
First, at time t0, RAS/ falls, and an X address XAD externally input from the address terminals ADD is taken in. This X address XAD is input to the address generator D and an internal X address XA is generated. This internal X address XA is input to the X decoder. The X decoder selects a word line selected by XA from among a word line group. Accordingly, WLi rises at almost the same time. After that, information for all memory cell units connected to WLi (a minute load) is transferred to one bit line of a bit line pair that has been previously charged to half the power supply voltage, namely VCC/2, and a minute potential difference is generated across all the complementary bit lines. This minute potential difference is amplified by a sense amplifier, and the potential difference across all the complementary bit lines is amplified to VCC.
At time t1 CAS/ falls, and a Y address YAD externally input from the address terminals ADD is taken in. This YAD is input to the address generator D and an internal Y address YA is generated and input to the Y decoder B. The Y decoder B selects, for exanple, column unit Ci selected by YA from among a group of column units. That is, Y decoder output Ydi rises, Trai, Trai/ are turned ON and information that has been amplified on the bit line pairs BLi, /BLi is transferred to the data buses D, D/. This information is transferred to input/output unit E through the data bus pair D, D/, and output from output terminals.
At time t4, CAS/ falls, and the-next Y address YAD from address terminals ADD is taken in, similarly to the situation at time t1 (here, the Y address is input incrementally). This YAD is input to address generator D, an internal Y address YA is generated and this internal Y address YA is input to Y decoder B. The Y decoder B selects column unit Ci+1 selected by YA, from among a group of column units. That is, Y decoder output Ydi+1 rises, Trai+1, Trai+1/ are turned ON and information that has been amplified on the bit line pairs BLi+1, /BLi+1 is transferred to the data buses D, D/. This information is transferred to input/output unit E through the data bus pair D, D/, and output from output terminals. Page mode reading of the DRAM section can be carried out by repeating the above operations.
At time t6, RAS/ and CAS/ rise, and WLi falls.
At time t7 Bli, BLi/ are equalized to a level of VCC/2, and are put in a reset state.
At time t8, the next RAS/ cycle begins.
Next, the operation of a SAM cycle (taking a read operation as an example) will similarly be described for each instant shown in FIG. 4.
When RAS/ is at a low level in the cycle prior to FIG. 4, DT/OE/ is in a low level cycle (called a data transfer cycle). In this cycle, information for all memory cells connected to a word line designated by an input X address is transferred in one go to data register Fi (where i=1.about.n, here Fi is a flip flop), after being amplified by the sense amplifier operation as has been described previously, by the rising of transfer signal PDT.
At time t2, SE/ falls, putting the device into serial access possible operation mode.
At time t3, in synchronism with the rising of SC immediately after the falling of SE/ at time t2, output YSD1 of the serial decoder F, corresponding to a Y address input during a data transfer cycle, rises, and data stored in the flip flop F1 is transferred to data buses H, H/ because Trbi, Trbi/ are ON. The transferred data is transferred to input/output unit G and output from terminals SI/O.
At time t5, in synchronism with the next rising of SC, data of an address that is the address accessed at time t1+1 (flip flop F1) is output from terminals SI/O by the same circuit operation as for time t3. (The output YSD2 of the serial decoder F rises, and data stored in the flip flop F2 is transferred to data buses H, H/ because Trb2, Trb2/ are on. The transferred data is transferred to the input/output unit G.) After that, serial output continues in synchronism with the rising of SC.
At time t7, SI/O is put in to a high impedance state by the rising of SE/.
Instead of a multiport DRAM such as that described above, an example using a Synchronous DRAM can also be considered. This synchronous DRAM has a page mode as fast as 80-100 MHz compared to the 40-50 MHz page mode of a general purpose DRAM, so it is possible to use the synchronous DRAM as both a graphics memory and a buffer memory even if it only has a single port, by taking advantage of the high speed and performing time divided processing.
However, when such a synchronous memory is used, the system is caused to operate at twice the conventional speed, and since time shared processing is carried out, design of a controller is extremely complicated and system operating margin design is also difficult.
In an image processor system, such as the foregoing digital still camera system, that carries out image processing using a buffer memory simultaneously with presenting an image on a CRT or liquid crystal display, etc., and has a restricted mounting area on a system port, using a two-port multiport DRAM and a buffer DRAM can not reduce the mounting area on a system port, and even if a synchronous DRAM is used design of a controller is extremely complicated.
It is therefore an object of present invention to provide a memory for use in a high performance digital still camera, that is easy to use and reduces the board surface area utility.